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data sheet the mark shows major revised points. mos integrated circuit m pd30200, 30210 document no. u10116ej7v0ds00 (7th edition) date published november 2000 n cp(k) printed in japan v r 4300 tm , v r 4305 tm , v r 4310 tm 64-bit microprocessor description the m pd30200-100, 30200-133 (v r 4300), 30200-80 (v r 4305), and 30210 (v r 4310) are high-performance, 64- bit risc (reduced instruction set computer) type v r series tm microprocessors employing the risc architecture developed by mips tm technologies inc. the v r 4300, v r 4305, and v r 4310 are intended for the high-performance embedded device field and have 32- bit system interface buses. detailed function descriptions are provided in the following users manual. be sure to read this manual before designing. ? v r 4300, v r 4305, v r 4310 users manual (u10504e) features ? employs 64-bit risc mips architecture ? high-speed operation processing ? 5-stage pipeline processing ? high-speed execution of integer and floating-point operations ? 48 specint92, 36 specfp92, 106 mips, at 80 mhz operation ( m pd30200-80) 60 specint92, 45 specfp92, 131 mips, at 100 mhz operation ( m pd30200-100) 80 specint92, 60 specfp92, 177 mips at 133 mhz operation ( m pd30200-133, m pd30210-133) 100 specint92, 75 specfp92, 221 mips at 167 mhz operation ( m pd30210-167) ? instruction set compatible with v r 4000 tm series (conforms to mips-i/ii/iii) ? on-chip cache memory (instruction: 16 kbytes, data: 8 kbytes) ? 32-bit address/data multiplexed bus facilitating system design ? low power consumption ? m pd30200-80: 1.5 w (typ.) (at 80 mhz operation) ? m pd30200-100, 30200-133: 1.8 w (typ.) (at 100 mhz operation), 2.4 w (typ.) (at 133 mhz operation) ? m pd30210- : 1.9 w (typ.) (at 133 mhz operation), 2.4 w (typ.) (at 167 mhz operation) ? supply voltage: 3.3 0.3 v ( m pd30200-80, 30200-100), 3.0 to 3.5 v ( m pd30200-133, 30210- ) unless otherwise specified, the v r 4300 ( m pd30200) is treated as the representative model throughout this document. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. 1995, 1998 1994
m pd30200, 30210 2 data sheet u10116ej7v0ds00 applications ? embedded controllers ? page printer controllers ? amusement game machines, etc. ordering information part number package maximum internal operating frequency (mhz) m pd30200gd-80-lbb 120-pin plastic qfp (28 28) 80 m pd30200gd-100-mbb 120-pin plastic qfp (28 28) 100 m pd30200gd-133-mbb 120-pin plastic qfp (28 28) 133 m pd30210gd-133-mbb 120-pin plastic qfp (28 28) 133 m pd30210gd-167-mbb 120-pin plastic qfp (28 28) 167
m pd30200, 30210 3 data sheet u10116ej7v0ds00 pin configuration (top view) ? 120-pin plastic qfp (28 28) m pd30200gd-80-lbb m pd30200gd-100-mbb m pd30200gd-133-mbb m pd30210gd-133-mbb m pd30210gd-167-mbb v dd gnd sysad22 sysad21 v dd gnd sysad20 v dd v dd p gndp pllcap0 pllcap1 v dd p gndp v dd (divmode2) masterclock gnd tciock v dd gnd syncout sysad19 v dd syncln gnd sysad18 sysad17 int4 v dd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 v dd gnd int2 sysad27 sysad28 v dd gnd sysad29 eok sysad30 v dd gnd pvalid sysad31 v dd gnd preq sysad0 v dd gnd sysad1 sysad2 v dd gnd sysad3 jtdo sysad4 jtdi v dd gnd 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 gnd v dd int3 sysad23 divmode0 sysad24 gnd v dd divmode1 syscmd4 coldreset syscmd3 gnd v dd syscmd2 evalid reset syscmd1 gnd v dd syscmd0 ereq sysad25 gnd v dd pmaster sysad26 nmi gnd v dd 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 gnd v dd sysad16 sysad15 gnd v dd sysad14 sysad13 gnd v dd sysad12 sysad11 gnd v dd sysad10 int0 sysad9 gnd v dd sysad8 sysad7 jtms gnd v dd sysad6 sysad5 jtck int1 gnd v dd remark ( ): pin name in the m pd30210-
m pd30200, 30210 4 data sheet u10116ej7v0ds00 pin names coldreset: cold reset divmode (1:0) note : divide mode eok: external ok ereq: external request evalid: external valid int(4:0): interrupt request jtck: jtag clock input jtdi: jtag data in jtdo: jtag data out jtms: jtag command signal masterclock: master clock nmi: non-maskable interrupt request pllcap (1:0): phase locked loop capacitance pmaster: processor master preq: processor request pvalid: processor valid reset: reset syncin: synchronization clock input syncout: synchronization clock output sysad(31:0): system address/data bus syscmd (4:0): system command/data id bus tclock: transmit clock v dd : power supply gnd: ground v dd p: v dd for pll gndp: gnd for pll note in the m pd30200- . divmode (2:0) in the m pd30210- .
m pd30200, 30210 5 data sheet u10116ej7v0ds00 internal block diagram cp0 tlb data, address system interface instruction cache clock generator data cache instruction address pipeline control execution unit control master clock
m pd30200, 30210 6 data sheet u10116ej7v0ds00 contents 1. pin functions ............................................................................................................ ................ 7 2. electrical specifications ................................................................................................ .. 9 3. package drawing ........................................................................................................... .......... 19 4. recommended soldering conditions ............................................................................... 20 appendix differences between the v r 4300, v r 4305, v r 4310 and v r 4100 tm .............. 21
m pd30200, 30210 7 data sheet u10116ej7v0ds00 1. pin functions pin name i/o function sysad (31:0) i/o system address/data bus. 32-bit bus for communication between processor and external agent. syscmd (4:0) i/o system command/data id bus. 5-bit bus for communication of commands and data identifiers between processor and external agent. evalid input external valid. signal indicating that external agent has transmitted valid address or data onto sysad bus and valid command or data identifier onto syscmd bus. pvalid output processor valid. signal indicating that processor has transmitted valid address or data onto sysad bus and valid command or data identifier onto syscmd bus. ereq input external request. signal used by external agent to request use of system interface. preq output processor request. signal used by processor to request use of system interface. if the processor detects a protocol error, this signal oscillates with the same frequency as sclock (internal), and the system interface hangs up. pmaster output processor master. signal indicating processor controls system interface. eok input external ok. signal indicating that external agent can accept processor request. int (4:0) input interrupt. general-purpose processor interrupt requests, the input status of which can be confirmed by bits 14 through 10 of cause register. nmi input non-maskable interrupt. interrupt request that cannot be masked. coldreset input cold reset. signal that initializes internal status of processor. it can be made active/inactive without synchronizing with the masterclock. reset input reset. signal that generates reset exception without initializing internal status of processor. masterclock input master clock. clock input signal to processor. tclock output transmit-receive signal clock this is the basic clock for the system interface and is synchronized with the masterclock. syncout output synchronization clock output. output of synchronization clock. syncin input synchronization clock input. input of synchronization clock. jtdi input jtag data input. input of jtag serial data.
m pd30200, 30210 8 data sheet u10116ej7v0ds00 pin name i/o function jtdo output jtag data output. output of jtag serial data. jtms input jtag command. indicates that input serial data is command data. jtck input jtag clock input. input of jtag serial clock. if the jtag interface is not used, set it to low level. divmode input mode setting. sets frequency ratio of masterclock, tclock, and pclock. ? divmode (1:0) (v r 4300) example divmode (1:0) masterclock pclock tclock ratio 00 33.3 mhz 133 mhz 33.3 mhz 1:4:1 note 1 01 66.7 mhz 100.0 mhz 66.7 mhz 2:3:2 note 2 10 50.0 mhz 100.0 mhz 50.0 mhz 1:2:1 11 33.3 mhz 100.0 mhz 33.3 mhz 1:3:1 notes 1. this setting is allowed with the 133 mhz model only. with the 100 mhz model, this setting is reserved. 2. this setting is allowed with the 100 mhz model only. with the 133 mhz model, this setting is reserved. ? divmode (1:0) (v r 4305) example divmode (1:0) masterclock pclock tclock ratio 00 66.7 mhz 66.7 mhz 66.7 mhz 1:1:1 01 C C C reserved 10 40 mhz 80 mhz 40 mhz 1:2:1 11 20 mhz 60 mhz 20 mhz 1:3:1 ? divmode (2:0) (v r 4310) example divmode (2:0) masterclock pclock tclock ratio 000 26.7 mhz 133 mhz 26.7 mhz 1:5:1 001 22.2 mhz 133 mhz 22.2 mhz 1:6:1 010 66.7 mhz 167 mhz 66.7 mhz 2:5:2 note 011 33.3 mhz 100 mhz 33.3 mhz 1:3:1 100 33.3 mhz 133 mhz 33.3 mhz 1:4:1 101 C C C reserved 110 50.0 mhz 100 mhz 50.0 mhz 1:2:1 111 33.3 mhz 100 mhz 33.3 mhz 1:3:1 note this setting is allowed with the 167 mhz model only. with the 133 mhz model, this setting is reserved. after power application, do not change the value of these pins; otherwise the operation is not guaranteed. pllcap (1:0) C pll capacitor. connect capacitor to adjust internal pll. v dd p C pll v dd . power supply for internal pll. gndp C pll gnd. ground for internal pll. v dd C positive power supply pin. gnd C ground pin.
m pd30200, 30210 9 data sheet u10116ej7v0ds00 2. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd C0.5 to +4.0 v input voltage note v i C0.5 to v dd + 0.3 v pulse of less than 10 ns C1.5 to v dd + 0.3 v operating case temperature t c 0 to +85 c storage temperature t stg C65 to +150 c note the upper limit of the input voltage (v dd + 0.3) is +4.0 v. cautions 1. do not short circuit two or more outputs at the same time. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the specifications and conditions shown in the following dc characteristics and ac characteristics are the range within which the product can normally operate and the quality can be guaranteed. dc characteristics (t c = 0 to +85 c, v dd = 3.3 0.3 v): m pd30200-80, 30200-100 (t c = 0 to +85 c, v dd = 3.0 to 3.5 v): m pd30200-133, 30210- parameter symbol conditions min. max. unit output voltage, high v oh i oh = C400 m a 2.4 v output voltage, high note 1 v ohc i oh = C400 m a 2.7 v output voltage, low v ol i ol = 2.5 ma 0.4 v input voltage, high v ih 2.0 v dd + 0.3 v input voltage, low v il C0.5 +0.8 v pulse of less than 10 ns C1.5 +0.8 v input voltage, high note 2 v ihc 0.8v dd v dd + 0.3 v input voltage, low note 2 v ilc C0.5 0.2v dd v pulse of less than 10 ns C1.5 0.2v dd v supply current i dd m pd30200 at 80 mhz operation 0.60 a at 100 mhz operation 0.67 a at 133 mhz operation 0.90 a m pd30210 at 133 mhz operation 0.69 a at 167 mhz operation 0.85 a input leakage current, high i lih v i = v dd 10 m a input leakage current, low i lil v i = 0 v C10 m a output leakage current, high i loh v o = v dd 20 m a output leakage current, low i lol v o = 0 v C20 m a notes 1. applied to the tclock pin. 2. applied to the masterclock pin only. remark the operating supply current is almost proportional to the operating clock frequency.
m pd30200, 30210 10 data sheet u10116ej7v0ds00 capacitance (t a = 25 c, v dd = 0 v) parameter symbol conditions min. max. unit input capacitance c in f c = 1 mhz 10 pf output capacitance c out unmeasured pins returned to 0 v. 10 pf ac characteristics (t c = 0 to +85 c, v dd = 3.3 0.3 v): m pd30200-80, 30200-100 (t c = 0 to +85 c, v dd = 3.0 to 3.5 v): m pd30200-133, 30210- clock parameters (1) m pd30200- parameter symbol conditions m pd30200-80 m pd30200-100 m pd30200-133 unit min. max. min. max. min. max. master clock high-level width t mckhigh 3.5 3.5 3.5 ns master clock low-level width t mcklow 3.5 3.5 3.5 ns master clock frequency note divmode = 1:1 20 66.7 CCCCmhz divmode = 1:2 20 66.7 20 66.7 34 66.7 mhz divmode = 2:3 C C 20 66.7 C C mhz divmode = 1:3 20 66.7 20 66.7 24 66.7 mhz divmode = 1:4 CCCC20 66.7 mhz master clock cycle t mckp divmode = 1:1 15 50 CCCCns divmode = 1:2 15 50 15 50 15 29 ns divmode = 2:3 C C 15 50 C C ns divmode = 1:3 15 50 15 50 15 41 ns divmode = 1:4 CCCC1550ns clock jitter t mcjitter 500 500 500 ps master clock rise time t mcrise 4.0 4.0 4.0 ns master clock fall time t mcfall 4.0 4.0 4.0 ns jtag clock cycle t jtagckp 4 t mckp 4 t mckp 4 t mckp ns note the operation of the internal pll of the m pd30200- is guaranteed. the rp mode is supported only by m pd30200-80 and 30200-100 and guaranteed when the master clock frequency is 40 mhz or higher.
m pd30200, 30210 11 data sheet u10116ej7v0ds00 (2) m pd30210- parameter symbol conditions m pd30210-133 m pd30210-167 unit min. max. min. max. master clock high-level width t mckhigh 3.5 3.5 ns master clock low-level width t mcklow 3.5 3.5 ns master clock frequency note divmode = 2.0 50 66.7 50 83.3 mhz divmode = 2.5 C C 40 66.7 mhz divmode = 3.0 33.3 44.4 33.3 55.6 mhz divmode = 4.0 25 33.3 25 41.7 mhz divmode = 5.0 20 26.7 20 33.3 mhz divmode = 6.0 20 22.2 20 27.8 mhz master clock cycle t mckp divmode = 2.0 15 20 12 20 ns divmode = 2.5 C C 15 25 ns divmode = 3.0 22 30 18 30 ns divmode = 4.0 30 40 24 40 ns divmode = 5.0 37 50 30 50 ns divmode = 6.0 45 50 36 50 ns clock jitter t mcjitter 500 500 ps master clock rise time t mcrise 4.0 4.0 ns master clock fall time t mcfall 4.0 4.0 ns jtag clock cycle t jtagckp 4 t mckp 4 t mckp ns note the operation of the internal pll of the m pd30210- is guaranteed. the rp mode is not supported by the m pd30210- . system interface parameters (1) m pd30200-80 (t c = 0 to 85 c, v dd = 3.3 0.3 v) parameter symbol conditions at 66.7 mhz input note 3 at 40 mhz input note 3 at 33.3 mhz input note 3 unit min. max. min. max. min. max. data output delay time note 1 t do c l = 50 pf 2.0 8.0 2.0 8.0 2.0 8.0 ns data setup delay time note 1 t ds 3.5 3.5 3.5 ns data hold delay time note 1 t dh 1.5 1.5 1.5 ns clock rise time note 2 t corise c l = 50 pf 4.0 4.0 4.0 ns clock fall time note 2 t cofall 4.0 4.0 4.0 ns clock high-level width note 2 t cohigh 3.5 8.5 11.0 ns clock low-level width note 2 t colow 3.5 8.5 11.0 ns notes 1. applied to all interface pins. 2. applied to tclock pin. 3. master clock frequency (example)
m pd30200, 30210 12 data sheet u10116ej7v0ds00 (2) m pd30200-100 (t c = 0 to 85 c, v dd = 3.3 0.3 v) parameter symbol condition at 66.7 mhz input note 4 at 62.5 mhz input note 4 at 50 mhz input note 4 at 33.3 mhz input note 4 unit min. max. min. max. min. max. min. max. data output delay time note 1 t do c l = 50 pf 2.0 8.0 2.0 8.0 2.0 8.0 2.0 8.0 ns data setup delay time note 1 t ds 3.5 3.5 3.5 3.5 ns data hold delay time note 1 t dh 1.5 1.5 1.5 1.5 ns mode data setup time note 2 t mds 3.5 3.5 3.5 3.5 ns clock rise time note 3 t corise c l = 50 pf 4.0 4.0 4.0 4.0 ns clock fall time note 3 t cofall 4.0 4.0 4.0 4.0 ns clock high-level width note 3 t cohigh 3.5 4.0 6.0 11.0 ns clock low-level width note 3 t colow 3.5 4.0 6.0 11.0 ns notes 1. applied to all interface pins (except divmode (1:0) pin). 2. applied to divmode (1:0) pin. 3. applied to tclock pin. 4. master clock frequency (example) (3) m pd30200-133 (t c = 0 to 85 c, v dd = 3.0 to 3.5 v) parameter symbol conditions at 66.7 mhz input note 4 at 44.4 mhz input note 4 at 33.3 mhz input note 4 unit min. max. min. max. min. max. data output delay time note 1 t do c l = 50 pf 2.0 8.0 2.0 8.0 2.0 8.0 ns data setup delay time note 1 t ds 3.5 3.5 3.5 ns data hold delay time note 1 t dh 1.5 1.5 1.5 ns mode data setup time note 2 t mds 3.5 3.5 3.5 ns clock rise time note 3 t corise c l = 50 pf 4.0 4.0 4.0 ns clock fall time note 3 t cofall 4.0 4.0 4.0 ns clock high-level width note 3 t cohigh 3.5 7.2 11.0 ns clock low-level width note 3 t colow 3.5 7.2 11.0 ns notes 1. applied to all interface pins (except divmode (1:0) pin). 2. applied to divmode (1:0) pin. 3. applied to tclock pin. 4. master clock frequency (example)
m pd30200, 30210 13 data sheet u10116ej7v0ds00 (4) m pd30210-133 (t c = 0 to 85 c, v dd = 3.0 to 3.5 v) parameter symbol conditions at 66.7 mhz input note 3 at 33.3 mhz input note 3 unit min. max. min. max. data output delay time note 1 t do c l = 50 pf 2.0 8.0 2.0 8.0 ns data setup delay time note 1 t ds 3.5 3.5 ns data hold delay time note 1 t dh 1.5 1.5 ns clock rise time note 2 t corise c l = 50 pf 4.0 4.0 ns clock fall time note 2 t cofall 4.0 4.0 ns clock high-level width note 2 t cohigh 3.5 11.0 ns clock low-level width note 2 t colow 3.5 11.0 ns notes 1. applied to all interface pins. 2. applied to tclock pin. 3. master clock frequency (example) (5) m pd30210-167 (t c = 0 to 85 c, v dd = 3.0 to 3.5 v) parameter symbol conditions at 83.3 mhz input note 3 at 66.7 mhz input note 3 at 33.3 mhz input note 3 unit min. max. min. max. min. max. data output delay time note 1 t do c l = 50 pf 1.5 8.0 1.5 8.0 1.5 8.0 ns data setup delay time note 1 t ds 3.5 3.5 3.5 ns data hold delay time note 1 t dh 1.5 1.5 1.5 ns clock rise time note 2 t corise c l = 50 pf 2.5 4.0 4.0 ns clock fall time note 2 t cofall 2.5 4.0 4.0 ns clock high-level width note 2 t cohigh 3.5 3.5 11.0 ns clock low-level width note 2 t colow 3.5 3.5 11.0 ns notes 1. applied to all interface pins. 2. applied to tclock pin. 3. master clock frequency (example) load coefficient rating parameter symbol conditions min. max. unit load coefficient cld 2 ns/25 pf
m pd30200, 30210 14 data sheet u10116ej7v0ds00 1.5 v t do 1.5 v sciock all output pins dut c l = 50 pf all output pins test conditions test load timing charts clock timing t mckhigh t mckp 0.5v dd masterclock t mcklow t mcrise 0.8v dd 0.2v dd t mcfall t cohigh tclock t colow t corise 0.8v dd 0.2v dd t cofall
m pd30200, 30210 15 data sheet u10116ej7v0ds00 sclock sysad (31:0) syscmd (4:0) (output) t do t dh t ds t do t ds t dh sysad (31:0) syscmd (4:0) (input) pvalid, preq, pmaster output input input evalid, ereq, eok, int0 to int4, nmi output clock jitter note if syncout and syncin are connected with the shortest path, the point of tclock = 50% is the point of masterclock = 50%. remark to match the masterclock edge, make the load capacitance of the syncin/syncout path the same as that of tclock. system interface edge timing 0.5v dd 0.5v dd t mcjitter masterclock tclock note t mcjitter
m pd30200, 30210 16 data sheet u10116ej7v0ds00 1 2 3 4 cycle masterclock (input) syncout (output) pclock (internal) sclock (internal) tclock (output) sysad driven (output) sysad received (input) data data data data data data data data t do t dh t ds clocking relationships
m pd30200, 30210 17 data sheet u10116ej7v0ds00 masterclock (input) coldreset (input) reset (input) divmode (1:0) note1 (input) syncout (output) tclock (output) t ds t dh t mds note 2 t ds 16 master clocks or more 64000 master clocks or more undefined undefined t dh power-on reset timing notes 1. in the m pd30200- . divmode (2:0) in the m pd30210- . 2. in the m pd30200-100 and 30200-133. t ds in the m pd30200-80 and 30210- .
m pd30200, 30210 18 data sheet u10116ej7v0ds00 masterclock (input) coldreset (input) reset (input) syncout (output) tclock (output) t ds t ds 16 master clocks or more 64000 master clocks or more undefined undefined t dh t dh masterclock (input) coldreset (input) reset (input) syncout (output) tclock (output) t ds t ds 16 master clocks or more h t dh t dh cold reset timing software reset timing
m pd30200, 30210 19 data sheet u10116ej7v0ds00 120 pin plastic qfp (28x28) note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. q s 0.1 0.1 3.3 0.2 p120gd-80-lbb, mbb-2 b c d f g h i j 28.0 0.2 2.4 2.4 0.37 28.0 0.2 k l 0.17 0.8 0.2 0.8 (t.p.) 0.15 2.0 0.2 m 0.1 32.0 0.3 n p 3.2 + 0.08 - 0.07 item millimeters a 32.0 0.3 r5 5 + 0.08 - 0.07 q r h m l p g f s m 90 91 61 60 130 120 31 s s a b cd i j k n detail of lead end 3. package drawing
m pd30200, 30210 20 data sheet u10116ej7v0ds00 4. recommended soldering conditions the products should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec representative. table 4-1. surface mounting type soldering conditions m pd30200gd-80-lbb: 120-pin plastic qfp (28 28) m pd30200gd-100-mbb: 120-pin plastic qfp (28 28) m pd30200gd-133-mbb: 120-pin plastic qfp (28 28) m pd30210gd- -mbb: 120-pin plastic qfp (28 28) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (at 210 c or higher), ir35-367-2 count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 36 hours.) vps package peak temperature: 215 c, time: 40 sec. max, (at 200 c or higher), vp15-367-2 count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 36 hours.) wave soldering solder bath temperature: 260 c max., time: 10 sec. max., ws60-367-1 count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 36 hours) partial heating pin temperature: 300 c max., time: 3 sec. max. (per pin row) C note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
m pd30200, 30210 21 data sheet u10116ej7v0ds00 appendix differences between the v r 4300, v r 4305, v r 4310 and v r 4100 tm parameter v r 4300 v r 4305 v r 4310 v r 4100 system bus write data transfer two buses (d/d ) four buses (d/d /d /d ) initial value setting divmode (1:0) divmode (2:0) bigendian, div2, pins at reset time (can be set on power application only) (can be set on power hizparity application only) block write access sequential ordering subblock ordering state after final final data retained in transfer rate setting end of access data write non-cache provided provided (set high-speed write with a register) cpu corresponding mips i, ii, and iii instruction sets mips i, ii, iii instructions instruction sets plus sum-of-products arithmetic cache memory data protection none word parity (instructions), byte parity (data) jtag interface provided none syncout-syncin path provided none clock interface input vs. internal 1.5 note 1 , 2, 3, 4 note 2 1, 2, 3 2, 2.5 note 3 , 3, 4, 4 multiplication rate 5, 6 internal vs. bus 1.5 note 1 , 2, 3, 4 note 2 1, 2, 3 2, 2.5 note 3 , 3, 4, 1, 2 frequency division 5, 6 rate power mode low-power mode pipeline/system bus operated at a none none quarter of the normal rate note4 wait mode none three types prid register imp = 0 0b imp = 0 0c notes 1. the 1.5 times frequency setting is allowed with the 100 mhz model only. (with the 133 mhz model, this setting is reserved.) 2. the 4 times frequency setting is allowed with the 133 mhz model only. (with the 100 mhz model, this setting is reserved.) 3. the 2.5 times frequency setting is allowed with the 167 mhz model only. (with the 133 mhz model, this setting is reserved.) 4. not supported by the 133 mhz model of the v r 4300.
m pd30200, 30210 22 data sheet u10116ej7v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. v r 4000, v r 4100, v r 4300, v r 4305, v r 4310, and v r series are trademarks of nec corporation. mips is a registered trademark of mips technologies, inc. in the united states.
m pd30200, 30210 23 data sheet u10116ej7v0ds00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
m pd30200, 30210 m8e 00. 4 the information in this document is current as of july, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). exporting this product or equipment that includes this product may require a governmental license from the u.s.a. for some countries because this product utilizes technologies limited by the export control regulations of the u.s.a.

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